Memory devices are used in a wide range of fields. For example, solid-state memory can be used for long or short term storage of program instructions and data in connection with computing devices. Memory density, access speed, and reliability are all important considerations in designing solid-state memory. Recent solid-state memory designs have used three-dimensional architectures. Such designs can increase memory density. In addition, such designs are well suited for use in connection with resistive random access memory (ReRAM), phase change random access memory (PCRAM), and phase change random access memory (PRAM).
In a three-dimensional (3D) memory structure, signal lines, including bit lines (BL) and word lines (WL), extend between socket regions on a periphery of the memory structure, and the memory array itself. More particularly, a first socket region on a first side of the memory array can include electrodes or contacts associated with the bit lines, and a second socket region on a second side of the memory array can include electrodes or contacts associated with the word lines. In other configurations, socket regions on first and second opposing sides of the memory array can be associated with bit lines, and socket regions on third and fourth opposing sides of the memory array can be associated with word lines. As the number of memory cells included in the memory array is increased, there is a corresponding increase in the number of signal lines (i.e. bit lines and/or word lines). In addition, due to physical constraints in the size of the bit lines and word lines, the area of the memory structure occupied by the socket regions becomes increasingly large as compared to an area of the memory array. This problem is exacerbated by decreases in the size of memory cells and in the size of memory cell pitch, and increases in the density of the memory array. The area of the memory structure occupied by socket regions also increases relative to the area of the memory structure occupied by the memory array as the number of decks or layers within the memory structure increases. Moreover, the complicated three-dimensional structure of such memories makes individual memory cells difficult to access. Because of such problems, decreases in the overall size of memory structures have not kept pace with decreases in the size of memory arrays themselves, and costs associated with providing three-dimensional memory structures have remained relatively high.